1. Field of the Invention
The present invention relates to a multi-layered ceramic capacitor, and more particularly to a thin film type multi-layered ceramic capacitor that can be miniaturized with high electrostatic capacity. Also, the present invention relates to a method of manufacturing the same.
2. Description of the Related Art
Generally, a multi-layered ceramic capacitor is a chip type capacitor having a plurality of stacked dielectric layers with electrodes printed thereon, which is widely used in electronic products. As the market for mobile communication devices and portable electronic devices expands, it is necessary that the size of the multi-layered ceramic capacitor be decreased and the capacity of the multi-layered ceramic capacitor be increased.
The conventional multi-layered ceramic capacitor is manufactured by stacking a plurality of green sheets with electrode paste applied thereto to form a stacked body and forming side electrodes at both sides thereof. With the above-mentioned bulk process, however, decrease of the size of the multi-layered ceramic capacitor and increase of the capacity of the multi-layered ceramic capacitor are limited.
In order to solve the above-mentioned problem, a brisk study of introducing a semiconductor thin film process has been made in the current multi-layered ceramic capacitor application. For example, a method of manufacturing a multi-layered ceramic capacitor has been proposed that is capable of depositing a (Ba,Sr)TiO3 film with high permittivity through the use of metal organic chemical vapor deposition (MOCVD), which is disclosed in Japanese Unexamined Patent Publication No. 2001-181839. FIG. 1 is a side view, in section, showing a conventional thin film type multi-layered ceramic capacitor manufactured using the above-mentioned manufacturing method.
As shown in FIG. 1, the conventional thin film type multi-layered ceramic capacitor comprises Pt electrode films 12 and 16 deposited on a substrate 11, such as MgO, through repetitive execution of a sputtering process, and a BST dielectric film 14 deposited on the substrate 11 through repetitive execution of metal organic chemical vapor deposition. The electrode films and the dielectric film are deposited through the sputtering process and the metal organic chemical vapor deposition, respectively, and the respective films are patterned through a photolithographic process and an etching process as shown in FIG. 1. In this way, the multi-layered ceramic capacitor is manufactured.
However, the conventional thin film type multi-layered ceramic capacitor is formed on the upper surface of the substrate, which is very limited. As a result, the effective area, which decides the electrostatic capacity, is limited. For this reason, the stacking process must be repetitively carried out to obtain high electrostatic capacity. Consequently, the photolithographic process and the etching process are increased, which complicates the overall process.
As described above, the conventional thin film type multi-layered ceramic capacitor has difficulty in obtaining high electrostatic capacity, for example, more than 10 μF, due to the limitation caused from the structure of the flat board.
A micro-structured capacitor using an SOI (silicon on insulator) substrate is also disclosed in U.S. Pat. No. 6,421,224, in which upper and lower silicon layers are etched using an insulating layer as an etching stop layer to provide uniform porosity to upper and lower silicon layers, and a dielectric film and a metal layer are formed on the etched upper and lower surfaces of the silicon layers to provide a three-dimensional micro-structured capacitor. A plurality of such micro-structured capacitors are stacked to provide a miniaturized capacitor with high electrostatic capacity. The micro-structured capacitor has the effect of increasing surface area through the porous structure and obtaining high electrostatic capacity through the stacked structure. However, the remaining silicon layer and the insulating layer, which is used as the etching stop layer, are left between upper and lower electrodes in addition to the dielectric film. As a result, the performance of the capacitor may be decreased. Also, the construction of input and output terminals is very complicated in the stacking structure.
Also, a method of manufacturing a semiconductor device including a plurality of memory cells wherein a plurality of holes are formed, and a thin film capacitor is formed at the surface where the holes are formed, is disclosed in U.S. Pat. No. 6,503,791. However, Pat '791 relates to a method of manufacturing a capacitor cell structure integrated into the semiconductor device, not to a method of manufacturing a single high-capacity capacitor.